The present invention relates to the electrical circuit control of a multiple number of indicator-switch elements only one of which is desired to be lit at one time, such as light emitting diode (LED) type indicator switches in a selection register of a digital computer.
Prior art structures exist for performing one of N selection through the use of pushbutton indicator-switches. Such a capability--that only one of a assemblage of N elements should be selectable at one time--is useful in the computer arts where one only of a number of sources is desired to be gated to a single destination, such as general display register. Since one of N selection for the purpose of selecting a single source to be gated for display often occurs at a computer indicator display maintenance or control panel, it is desirous to interface one of N display selection occuring at switches, normally indicator-switches, to the remotely situated logic elements by but an economical single wire per each of the N selectable alternatives. The prior art also encompasses this single wire interconnection economy.
The inadequacy of prior art structures is not manifest until N becomes large, meaning that many indicator-switches exist to each selectably enable the display in a single register of a uniquely associated situs or quantity. In support of improved visibility of computer registers and control sites for the purposes of maintenance, it is not unusual to selectably individually gate dozens of different registers to an economical joint display area. This display selection may be effectuated by an encoded register selection, but this requires that the user-operator recall and apply some arbitrary addressing protocol for display selection. It is much to be preferred, even with the attendent proliferation of selection pushbutton switches, that a user-operator should merely touch a labeled switch to select exactly what he/she wants to be displayed in a general register. The prior art logics which support this selection consists of cross-connected AND gates, one associated with each of the N selections. The output of each gate is routed to the input of all others. If one only AND gate output is emplaced in the logical state enabling selection of the associated one of the N selectable registers, as by a switch action then that selfsame output will disable all other AND gates, disabling selection of the associated registers. This straightforward prior art scheme requires N AND gates, or tiered AND logics, having N-1 input signals each. Obviously when N becomes large these requisite N-1 input signals are not supportable by a single AND gate, and a proliferation of logical gates into a tiered structure performing the logical AND function is required. This multiplication of the 1 of N control logics with increasing N is the deficiency of prior art logics, especially for large N.